CIS TSV packaging process

The TSV packaging process of CIS (CMOS Image Sensor) is a silicon through hole process belonging to the narrow concept of TSV. Through silicon perforation, the upper and lower lines are connected to achieve the purpose, and it has not risen to the height of 3D integration, which is different from the concept of TSV system integration mentioned by SiP in the industry. But CIS packaging is an important part of the sealing process at present

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What exactly is wafer-level Packaging (WLP)?

Wafer-level packaging (WLP) is the packaging process in which most of the process is operated on the wafer (large wafer), the demand for wafer-level packaging (WLP) is not only subject to the requirements of smaller package size and height, but also must meet the requirements of simplifying the supply chain and reducing the overall cost, and improving the overall performance.

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Detail the Gate-All-Around transistor technology in TSMC's 2 nm process

First adopted by Intel at the 22nm node, fin-field-effect transistors (FINFETs) have become the dominant architecture of semiconductor devices over the past decade. However, after the 5 nm node, the fin structure is difficult to meet the electrostatic control required by the transistor. The leakage phenomenon worsens sharply when the size is further reduced. Therefore, the semiconductor industry urgently needs a new solution to replace the finned transistor structure in the nodes of the future.

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WLP

Wafer Level Package (WLP) is a modified and enhanced CSP based on BGA technology. Some people also refer to WLP as chip level Chip Size Package (WLP-CSP). Wafer-level packaging technology takes wafers as processing objects, packages, ages and tests many chips on wafers at the same time, and finally cuts them into a single device, which can be mounted directly to the substrate or printed circuit board. It reduces the package size to the size of the IC chip, and the production cost is greatly redu

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