Detail the Gate-All-Around transistor technology in TSMC's 2 nm process

First adopted by Intel at the 22nm node, fin-field-effect transistors (FINFETs) have become the dominant architecture of semiconductor devices over the past decade. However, after the 5 nm node, the fin structure is difficult to meet the electrostatic control required by the transistor. The leakage phenomenon worsens sharply when the size is further reduced. Therefore, the semiconductor industry urgently needs a new solution to replace the finned transistor structure in the nodes of the future.

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WLP

Wafer Level Package (WLP) is a modified and enhanced CSP based on BGA technology. Some people also refer to WLP as chip level Chip Size Package (WLP-CSP). Wafer-level packaging technology takes wafers as processing objects, packages, ages and tests many chips on wafers at the same time, and finally cuts them into a single device, which can be mounted directly to the substrate or printed circuit board. It reduces the package size to the size of the IC chip, and the production cost is greatly redu

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Solutions to prevent X-ray damage to Flash Memory

At present, due to the rising storage density of Flash Memory storage devices and the continuous updating of chip production process nodes, the process within 20 nm is becoming more and more common in the manufacturing of memory devices. The continuous expansion of line width not only brings challenges to manufacturing, but also brings new challenges to the X-ray inspection during the assembly process. The experiment proves that the memory chip will lose the data due to the electronic transition

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